The disclosed embodiments of the present invention relate to a method for flip chip packaging co-design, and more particularly, to a method for flip chip packaging co-design which can provide a bi-directional flip-chip co-design flow, analyze chip-aware bump pitches, simulate IR-aware bump counts/locations, speed up design cycle, as to increase design quality, and lower design cost.
Conventional methods of using regular bump patterns to do flip-chip co-design have already been disclosed and discussed in various literatures, such as U.S. Pat. No. 7,117,467. However, the conventional methods do not consider Input/Output (I/O) pad and/or redistribution layer (RDL) requirements and cannot handle non-uniform power domains to improve IR drops since the I/O information, the RDL routing information, and/or the power domain information of the chip and the connection information of a PCB are not provided in advance.
Therefore, the conventional methods require more design cycles and larger chip size, and result in worse IR drops.